The present invention relates to integrated circuit packaging, and, more particularly, to an integrated circuit package with a novel wire-bond finger layout.
Most very large scale integrated (VLSI) circuits are fabricated on small silicon or other crystalline substrates. Sophisticated packaging is required to provide electrical interfacing with and protection for these devices. The demands on the integrated circuit package are increased as the required number of input/output and power connections reaches into the hundreds.
The multilayer ceramic pin-grid array (PGA) is recognized as a most suitable technology for ultradense pin layouts. Conductive paths are formed by screen printing metallization patterns on unfired alumina tape or "green sheets". Interlayer connections are made through via holes which are punched out and filled with a paste of conductive material such as aluminum or tungsten. The green sheets are laminated and co-fired to form a monolithic package with complete electrical paths or "fingers" between pin locations and bonding pads located on a ceramic bonding shelf.
A package so constructed generally includes a central cavity in which an integrated circuit silicon die can be attached using a gold-silicon eutectic, other hard or soft solder, a silver glass paste or other bonding material. The die is electrically interfaced to the package using bonding wires which extend between bonding pads on the die to respective bonding pads on the bonding shelf. Typically, it is convenient to arrange both the die bonding pads and the package bonding pads in square rows so that the bonding wires can be positioned straight across the gap between the die and the shelf.
To a point, an increased pin count can be accommodated by decreasing the pitch of the package bonding pads. However, every production technology imposes some minimum practical pitch. For example, a production technology may not permit bonding pads smaller than 5 mils square. Smaller pads may exceed the precision of available automated wire bonding equipment, or impair the reliability of the conductive nature of the bonding pad itself.
Partial solutions to this problem include radially spreading or fanning the wire bonds so that the bonding pads of the package are on a greater pitch than the bonding pads on the die. This can yield an about 20% practical improvement in pin count. Further increases involve using longer bonding wires than is practical or desirable. Also, the fan arrangement requires each wire to be bonded at a different angle.
Another approach uses multiple rows of package bonding pads, each on a separate bonding shelf located on a separate tier level. Each tier level is defined by an area of a ceramic layer protruding beyond an adjacent layer. By stair-stepping the ceramic layers multiple bonding shelves can be formed. For example, two bonding shelves can each be used to define a square row of package bonding pads at the minimum practical pitch, thus, doubling the pin count that can be accommodated with a single bonding shelf. Typically, the rows are staggered to optimize the spacing of the wires from adjacent die bonding pads.
The two bonding shelf approach has disadvantages. One problem is in the coregistration of the multiple rows of bonding pads. If the staggering is inexact, the likelihood of the bare bonding wires contacting and shorting is greatly increased. There are several contributors to such misalignment.
The major source of misalignment is uneven shrinkage during the co-firing of the ceramic package, which can involve heat exposure at 1500.degree. C. for about 48 hours. Shrinkage can amount to 17%-23% of the area of any given layer, and adjacent layers can shrink in different directions. Furthermore, any problem with shrinkage misalignment is exacerbated when intermediate layers are involved. In addition to misalignment due to shrinkage, the screen printing process introduces alignment errors at each layer.
What is needed, then, is a practical and economical approach to increasing the pin count that can be accommodated by a packaging scheme without the problems due to layer misalignment.